1. Field of the Invention
The present invention relates generally to digital Doherty transmitters, and, more particularly to an extended bandwidth digital Doherty transmitter.
2. Related Art
To cope with the ever-increasing number of wireless networks users, modem wireless communication standards (3rd generation and beyond) employ spectrum efficient modulation and access techniques, such as quadratic amplitude modulation (QAM), orthogonal frequency division multiplexing (OFDM) and code division multiple access (CDMA). Although these techniques permit an efficient management of the overcrowded radio frequency (RF) spectrum, they also result in creating highly varying envelope signals that are characterized with high peak-to-average power ratio (PAPR). To avoid signal clipping and loss of transmitted information through distortion during power amplification, the transmitter should handle the peak values of the transmitted signal even though it mostly operates at significantly lower average power levels. Accordingly, the power amplifier (PA) of wireless transmitter is forced to operate at large back-off from its saturation point where the power efficiency of the PA drops drastically.
A popular power amplification architecture for enhancing the efficiency at backed-off output power region is the Doherty amplifier architecture. Fundamentally, a Doherty amplifier is composed of: 1) one main amplifier (commonly denoted as carrier amplifier) that is operating in class-AB and performing signal amplification for all input signal levels, 2) at least one auxiliary amplifier (commonly denoted as peaking amplifier) that is operating in class-C and performing signal amplification starting from a predefined signal level, 3) an input analog power divider for splitting the input signal between the carrier amplifier and the peaking amplifier(s), 4) a non-isolated Doherty output power combiner for combining the outputs of the carrier amplifier and the peaking amplifier(s) which includes quarter wavelength transformers, and 5) 50 Ohms lines inserted at the input of the peaking amplifiers and/or carrier amplifier to balance the delay between the branches of the Doherty amplifier. The use of a non-isolated power combiner initiates an active load modulation mechanism that is based on dynamically changing the load presented to the carrier amplifier through the impedance modulation triggered by the peaking amplifier(s). This allows the carrier amplifier to operate efficiently until it reaches its optimal load while the peaking amplifier(s) is/are simultaneously contributing to the output power of the Doherty amplifier.
Practically, the two-stage Doherty amplifier which consists of one carrier amplifier and one peaking amplifier; and, the three-stage Doherty amplifier which consists of one carrier amplifier and two peaking amplifiers are the most used architectures in Doherty based RF transmitters. Practical implantations of four-stage and higher order-stage Doherty amplifiers are rare and not fully convincing in their performance. The main reasons are the rather complex design and the excessive costs of implementation for no significant performance improvement as compared to the two or three-stage Doherty amplifier architecture.
Ideally, two-stage (three-stage) Doherty amplifier has two (three) maximum efficiency points located within a range of up-to 6 dB (12 dB) of output power back-off relatively to the saturation output power point. This feature makes the two-stage and three-stage Doherty amplifiers the most suitable architectures for power amplification in 3rd generation and beyond wireless communications applications where the PAPR of the modulated signals is typically ranging between 6 and 12 dB. In practice, two-stage Doherty amplifiers are more suitable when the PAPR is about or slightly higher than 6 dB and three-stage Doherty amplifiers when the PAPR of the signal is significantly higher that than 6 dB. The achievement of such a superior performance requires a quasi-perfect load modulation mechanism which is not likely to happen in fully-analog implementations due to limitations related to inherent hardware impairments in the RF blocks of two-stage or three-stage Doherty amplifiers.
In the case of two- or three-stage Doherty amplifier, the dissimilarity in class of operation of the carrier amplifier and the one or two peaking amplifiers results in complex gain fluctuation between the output branches of the Doherty amplifier. As a result, the output signal amplitude from the carrier amplifier and the output signal amplitudes from peaking amplifiers do not match with the ideal current profiles governing the correct operation of the Doherty amplifier. This translates into an imperfect load modulation mechanism and degraded efficiency.
In a number of device (transistor) technologies (such as high electron-mobility transistor (HEMT) and gallium nitride (GaN), etc.), the difference in bias conditions between the carrier amplifier and peaking amplifiers results in power-dependant and highly nonlinear phase misalignment within the output branches of the Doherty amplifier which causes severe output power loss, deficient load modulation and degraded efficiency.
Another problem related to the Doherty PA is the narrow bandwidth performance. Indeed, due to the need for using quarter-wavelength impedance transformers to design the output power combiner, the efficiency of the Doherty PA drops significantly as the frequency of operation shifts away from the design frequency of the Doherty PA (f0), which greatly limits its bandwidth.